For integrated circuits i.e., circuits having multiple active elements formed on a silicon substrate, the formation of the circuits on the silicon substrate is only part of the fabrication procedure. The silicon substrate with its subsequent layers added during device formation generally has outermost surface regions—pads—of high electrical conductivity, i.e. conductivity greater than 0.02 (μohm-cm)−1 employed for electrical communication with the integrated circuit. Electrical connection to these pads and the protection of the silicon substrate with its added layers i.e. in totality, the die, is denominated in the trade as packaging.
A variety of methods have been used to connect the die to electronic circuitry external to the die such as by forming an interface between a die package and an external substrate or forming an interface directly to a circuit board e.g. printed circuit board. The two most commonly used interfaces from die to external substrate or circuit board are wirebonding and flip chip solder bumps. Wirebonding uses a wire, e.g. a gold wire, connection between the die pad and the external substrate pad or circuit board pad. Flip chip solder bumps connect the die pad to the external substrate pad or the circuit board pad via solder e.g. metal alloys such as Sn—Pb, Sn—Ag—Cu or Sn—Ag. These conducting masses are typically spherical in shape and are generally denominated solder bumps. (Although the connecting entities are termed solder bumps, the material of these bumps need not be solder but are formed from material that is electrically conducting. Similarly the shape of the entities need not be spherical, even though solder bumps are generally spherical in nature, more precisely truncated spheroids, since such shape is thermodynamically preferred. Other materials have other preferred stable states. For example, copper is more readily manufacturable in a cylindrical shape.) The connecting bumps, in the context of this disclosure generically referred to as solder bumps, are employed to produce an electrical pathway to other entities.
In a common approach, the desired electrical connection is produced by physically abutting the solder bumps of the integrated circuit die with a corresponding array of electrically conducting bodies (also referred to for purpose of this disclosure as pads) formed on a body external to the die e.g. an external substrate and/or a rigid or flexible circuit board. Generally, the array on the integrated circuit die and the mating array on the external body are formed in a geometric grid pattern. However, the geometry of the array is not critical and any configuration is considered for purposes of this disclosure as an array. Additionally, although the conducting array of the external substrate generally has a mating conducting region corresponding to each bump of the die such one to one correspondence is not required. The correspondence is chosen to effectuate the electrical connections necessary to produce the desired electrical circuit. The array of bumps formed from solder is mated with the pad array of the external body. This interconnection provides both an adequate mechanical and electrical connection. A typical assembly sequence for connecting a solder bumped die to a rigid or flexible substrate includes: 1) abutting the solder bumps with the substrate using flux as an intermediary, and 2) heating the assembly above the liquidus temperature of the solder. For example, heating is accomplished by employing temperatures in the range 217 to 260 degrees C., for commonly used lead-free solders typically containing Sn, Cu, and Ag and 183 to 225 degrees C. for eutectic Pb—Sn solders. Accordingly, a metallurgical joint is created between the solder and the die pads as well as between the solder and the external body pads. For improved mechanical and environmental stability, the joint is typically reinforced with a polymeric material (denominated an underfill) between the die and the substrate.
Nevertheless, despite these precautions, significant mechanical forces that cause deformation of the assembly are possible. Such forces are a consequence of the variety of materials constituting the assembly components and their corresponding differing thermo-mechanical properties, e.g. modulus and coefficient of thermal expansion. Additionally, differences in die size, substrate size, bump dimensions, material thicknesses only augment the difficulty in avoiding assembly deformation. (Although it is possible that there is no difference between the die and the external substrate in either stiffness and/or coefficient of thermal expansion, such circumstances are coincidental and quite unusual.) Further, even if the mechanical forces of a die/external body combination are tolerated at one operating temperature, mechanical failure of the combination is still a real possibility due to ambient temperature changes associated with transport or operation.
Mechanical distortion and/or failure, i.e. delamination or cracking at a material layer interface or cohesive failure within a material layer, is a real concern and often is the cause of, or contributing factor to, failure of an electronic component. Since the materials used in the die/external body assembly are generally dictated by a variety of electrical and mechanical demands associated with other problems there has been little flexibility in expedients used to maintain mechanical stability of the die/external body combination. In addition commercial considerations are driving the technology towards use of thinner material layers that, in turn, allow increased bending and thus increased mechanical stresses and strains experienced by the die/external body structure. An approach that mitigates the risk for failure due to thermomechanically induced loads for a reasonable spectrum of operating conditions and die/external body configurations would be quite desirable.